The minimum operational supply voltage (Vccmin) is an important parameter of today's processors. Reducing Vccmin is an important way to reduce the power consumption of a processor. Register files (RF) inside the processor are the limiting blocks in reducing Vccmin. RF Vccmin is typically the maximum of three components: write Vccmin, read Vccmin, and retention Vccmin. For register file cells, write Vccmin may be the worst of the three.
An example schematic diagram of a conventional 8-transistor RF cell is given in FIG. 1. In a write operation, the two write bit-lines (WRBL and WRBL#) are complementarily driven according to the data to be written into the cell. The write word-line (WRWL) is then set high so that data are written into the complementary nodes C1 and C2 of the RF cell via the write pass transistors PG1 and PG2, respectively. Unfortunately, a contention issue between the pass gate transistor (PG1 or PG2) that is to write a '1 into the cell and its associated pull-up transistor (P1 or P2, respectively) can occur, especially as the Vccmin level supplying the cell goes down.
A processor contains a very large number of RF cells. As a result, the statistical variations in the transistor characteristics can be as large as 5 or 6 times their standard deviations. Such statistical variations in the transistors of the cell can cause the pass gate transistor (PG1, PG2) to become too weak and the pull-up transistor (P1, P2) to become too strong, which may exacerbate the contention issue. As a result, such statistical variations may limit the Vccmin at which the cells can function properly.
Several approaches have been proposed to redress this issue. The traditional approach is to increase the sizing of the cell transistors either to make the pass NMOS transistors stronger or to reduce the statistical variations. However, this approach results in additional area, cost, and leakage power that are undesirable. Accordingly, new approaches to enable the reduction RF cell Vccmin may be desired.